The present invention relates generally to computer architectures. More particularly, the invention is directed to the architecture and use of registers within a super scalar computer.
The evolution of computer architectures has transitioned from the now broadly accepted reduced instruction set computing (RISC) configurations to super scalar computer architectures. Such super scalar computer architectures are characterized by the presence of multiple and concurrently operable execution units integrated through a plurality of registers and control mechanisms. The objective of the architecture is to employ parallelism to maximize the number of instructions concurrently processed by the multiple execution units during each interval of time, while ensuring that the order of instruction execution as defined by the programmer is reflected in the output. For example, the control mechanism must manage dependencies among the data being concurrently processed by the multiple execution units, the control mechanism must ensure that integrity of sequentiality is maintained in the presence of precise interrupts and restarts, and the control mechanism must provide instruction deletion capability such as is needed with instruction defined branching operations, yet retain the overall order of the program execution. The objectives are always sought mindful of the commercial objectives of minimizing electronic device count and complexity, where the prevailing convention in the context of the super scalar architecture is to reduce the size and content of the registers and the bit size of the words used for control and data transmission among the circuits.
A variety of architectures have been devised to manage the out-of-order execution of instructions. One example is the architecture and mode of operation described in U.S. Pat. No. 4,722,049, which architecture generally reorders instructions in a queue to optimize the use of a scalar/vector pair of execution units. A more relevant architecture and method of use is described in the article entitled "The Metaflow Architecture" authored by Popescu et al as appeared in the June, 1991 issue of IEEE Micro. This article provides an overview of contemporary super scalar architecture principles in the context of the problems characterizing out-of-order execution of instructions. The authors of the article also introduce the principles which underlie their implementation of an out-of-order instruction processor composed of multiple execution units, an architecture which utilizes a shelving concept to selectively defer instruction processing so as to meet the fundamental objective of having the instruction results reflect the order defined by the programmer. Two other techniques, commonly referred to as "scoreboarding" and the "Tomasulo algorithm" of dynamic scheduling are described in the textbook Computer Architecture A Quantitative Approach by Patterson et al, copyright 1990. A third technique, "register renaming", is disclosed and illustrated by example in U.S. Pat. No. 4,992,938. Thus, though the benefits of out-of-order instruction execution using multiple execution units are acknowledged, the architectures and methods for accomplishing the objectives have yet to be refined to an industry accepted.
Examples of fundamental constraints which limit super scalar architectures and practices include, the management of data dependencies among data being concurrently processed in multiple execution units, the ability to handle precise interrupts and restarts while maintaining the integrity of the instruction sequence, and the ability to selectively delete instructions for branching purposes or the like. Though such features are attainable, the complexity and hardware costs have heretofore been quite significant. For example, the deferral of instruction processing through the practice of shelving or reserving, as noted in the prior art, requires significant memory for instruction storage as well as resources for controlling the selective deshelving of instructions. Furthermore, the prior art use of information which relates shelved or reserved instructions both among themselves and to the control resources significantly increases the size of the control word subject both to storage and processing by the execution units. Therefore, there remains a need for a super scalar architecture in which multiple execution units concurrently process out-of-order instructions with minimum memory register and control resources.